Many factors contribute to the cost of manufacturing semiconductor chip packages. Because the development and high volume implementation of new semiconductor chip packages is typically a very expensive and involved process, one important factor is whether the new invention can be implemented using the existing packaging equipment infrastructure or whether specialized equipment must be created in order to practice the invention. If existing packaging equipment may be adapted to manufacture a new chip package, a large amount of money may be saved in implementing the new package. Further, many of the technological challenges in implementing high volume manufacture of a new packaging invention may be more easily overcome if existing equipment or processes can be changed to manufacture the new invention. This is because existing equipment and processes have known limitations within which the new packaging problems can be solved; while the limitations of new equipment or processes may not be so easily recognized or appreciated.
A packaging solution broadly accepted within the semiconductor industry is to use a tape automated bonding ("TAB") process to interconnect the contacts on a semiconductor chip to a package or lead frame. In a typical TAB process (as shown in FIGS. 1A-D), portions of a flexible dielectric supporting tape 10 are removed by a punching operation to create an opening 20. A layer of rolled and annealed copper 30 is then laminated to the tape 10 by adhesive 40. A first dielectric photo-resist 50 is then selectively applied to the top surface of the copper layer 30 and a second dielectric photoresist 60 is applied to the bottom exposed surfaces of the tape 10 and the copper layer 30. The exposed copper layer 10 is then etched so that only the copper leads 35 remain. The dielectric resist 50/60 is then removed leaving a central opening where the central tape portion 70 was positioned before it was unattached due to the etching step. The copper leads 35 thus extend into the central opening of the tape 10 such that the innermost ends of the leads 35 are self-supporting and cantilevered therein. The central opening is further generally slightly larger than a semiconductor chip to be attached thereto. The innermost ends of the leads 35 are arranged side by side at a spacing corresponding to the spacing of the contacts on the chip. The chip is then centered within the opening so that the innermost ends of the leads extend over the front or contact bearing surface on the chip. The innermost ends of the leads are then either gang bonded or single point bonded to the contacts of the chip using ultrasonic, thermosonic or thermo-compression bonding techniques, forming and defining what is referred to as the inner lead bond ("ILB"). One early bumpless TAB solution is disclosed in U.S. Pat. No. 3,390,308 issued to Marley in which a TAB-like lead structure for a multi-chip circuit assembly has cantilevered ribbon leads which are made flexible by having a thin cross section in an attempt to minimize the stress on the lead/contact bonds due to the differential thermal expansions and contractions between a chip and a heat sink, as described more fully below.
TAB and TAB leads have several known limitations, such as producing a chip package which has leads that are "fanned out" from the chip contacts to the periphery of the package creating a total chip package which is appreciably larger than the operational chip itself. Another known TAB problem is alignment and bonding of the leads to their respective chip contacts to form the ILBs. Because TAB leads are essentially free-floating, cantilevered conductive strips it is very difficult to rapidly and accurately bond a TAB lead to a particular chip contact while ensuring that the lead will not electrically short with adjacent leads or adjacent chip contacts. This is especially true with fine pitch (small center-to-center distances) TAB leads.
Further, TAB leads are typically comprised of copper because copper is readily available, easily processed by plating or etching, inexpensive, can be made to be pliable and yet still has acceptable conductivity. However, an oxidation film can form on the surface of copper leads over time thereby inhibiting both the conductivity of the lead and the strength of the bond between the lead and the chip contact. Compatibility of materials has also been a problem. For example, copper leads do not generally bond well with a chip contacts, which are typically made of aluminum or an aluminum alloy. Because of these material incompatibilities, boundary layers between the copper leads and the aluminum chip contacts have been used. One example of such a boundary layer is to use a gold "bump" typically placed between the ILB of the TAB lead and its respective chip contact. The bumps are either attached to each of the chip contacts or to the ends of the inner leads. Another solution, U.S. Pat. No. 4,188,438 issued to Burns, discloses the use of a thin anti-oxidant coating on copper TAB leads to obtain better copper to copper thermocompression bonds to chip bonding bumps. The anti-oxidant coating is used to inhibit the formation of an oxide layer from forming on the copper leads and the copper bonding pads; however, the anti-oxidant layer is also thin enough to allow a thermocompression bond to be obtained between the copper lead and the bonding bumps therethrough.
Incompatible lead and lead boundary layer materials can also cause problems. As stated above, TAB leads are typically comprised of copper for a variety of reasons. When a boundary layer is placed onto the lead to stop oxidation, one must be careful to use a boundary material which has an acceptable conductivity while at the same time ensuring that the lead material will not diffuse into the boundary material under the high temperatures used in chip packaging. Such diffusion generally creates a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients). These voids along the boundary of the two metals cause bond degradation between the metal layers and brittleness of the lead itself. For example, U.S. Pat. No. 4,842,662 issued to Jacobi describes another bumpless TAB solution, similar to the Marley ('308) patent described above. In the '662 patent the TAB lead is bent down toward the contact on a semiconductor chip preferably using a copper lead having a gold layer plated therearound. However, such copper-gold lead boundaries have been known to become unreliable because of the voiding problem. U.S. Pat. No. 5,384,204 issued to Yumoto et al. attempts to address this same issue with copper-tin TAB leads. This patent discloses forming at least one barrier layer between the copper lead and the tin layer such that the copper does not diffuse into the tin when the lead is bonded to a gold bumped semiconductor chip contact using a high temperature gold-tin eutectic bond process.
A still further known TAB package problem is compensating for the expansion rate differential ("thermal mismatch") between the chip and its supporting substrate during the heating and cooling cycles of the chip ("thermal cycling"). TAB leads are typically used internally in a chip package to interconnect the chip contacts to a lead frame. The combination is then generally encased in rigid plastic or epoxy such that the lead frame extends beyond the boundary of the encasement to a circuitized supporting substrate. Because of the length of the individual lead frame arms, the lead frame compensates for the effects of the thermal cycling by allowing the arms to bend and twist as the chip heats and cools. However, this creates a larger total chip package than is desired in many present day applications.
Despite the substantial time and effort devoted heretofore to the problems associated with providing an inexpensive yet reliable package lead, there are still unmet needs for improvements in such semiconductor chip package structures and methods.